The present invention relates generally to processes for fabrication of semiconductor integrated circuit devices and more particularly to a process for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates.
The use of advanced semiconductor processing techniques, for example improved etching and photolithographic procedures, has enabled the reduction in the dimensions of semiconductor devices and a concomitant increase in their operating speed. However, this reduction in dimensions has caused a corresponding decrease in the cross-sectional area of interconnect regions which in turn has caused an increase in interconnection time delay resulting from material and circuit parameters.
One solution to this increase in interconnection time delay is set forth in U.S. Pat. No. 4,180,596, issued Dec. 25, 1979 to Crowder et al. This solution comprises a method of placing a metal silicide layer on top of a doped polycrystalline silicon substrate in order to lower the sheet resistance of the polycrystalline silicon interconnections and gain increased circuit speed.
Although the addition of the metal silicide layer on top of the polycrystalline layer lowers sheet resistance causing an increase in circuit speed, the dopants introduced into the polycrystalline silicon substrate tends to diffuse out from the substrate into the metal silicide layer during subsequent annealing and/or oxidation of the device. This causes the underlying polycrystalline silicon layer to become highly resistive; which, in turn makes the contact properties uncontrollable and creates undesirable effects on the operation of a device.
A deleterious effect of this out-diffusion of the dopant from the polycrystalline silicon substrate into the metal silicide layer is shown in FIG. 1. As diagrammatically depicted in FIG. 1A, a conduction layer 100 of a refractory metal silicide is formed, for example, by co-depositing an amorphous layer of tantalum and silicon on a polycrystalline silicon (poly Si) substrate 102 which has been doped with boron in this example. After annealing at 950.degree. C. for one hour in hydrogen, the conductive layer 100 is converted into tantalum disilicide (Ta Si.sub.2). However, as diagrammatically represented by region 104 in FIG. 1B, boron depletion occurs at the tantalum disilicide/poly Si interface. As the boron diffuses into the tantalum disilicide layer 100, the interfacial region goes from p+ (represented diagrammatically by region 106 in FIG. 1B) to p- (represented by region 104) and the diode series resistance becomes excessively high. A similar effect occurs in the case of polycrystalline silicon base transistors where the base resistance increases due to boron out-diffusion to intolerably high levels, rendering the device inoperable. This phenomenon is shown in FIG. 1C which depicts a plot of resistivity as a function of distance from the surface of the device (resistivity/depth profile). As can be seen by the dotted curve, which sets forth the resistivity/depth profile after the annealing process, the resistivity at the disilicide/poly Si interfacial region increases substantially over that plotted for the initial profile.
FIG. 2 shows the deterioration in performance of the diode characteristics of a semiconductor device which experiences this dopant out-diffusion. As can be seen in FIG. 2A, the dopant out-diffusion (represented by arrow "d") manifests itself as a resistance R in series with the diode, as shown schematically in FIG. 2B. This causes a degradation in the characteristic current versus voltage curve of the device as shown in FIG. 2C.